First Workshop on Open, Programmable, and Emerging Networking Technologies for HPC and AI (OPENET4HAI)

Overview

The rapid evolution of HPC and AI systems is driving innovation across the entire communication stack, from networking hardware and programmable data and control planes to communication libraries, collective communication frameworks, runtime systems, and application-level communication optimization. Emerging smart network devices provide new opportunities across the entire stack for HPC and AI infrastructures.

This workshop aims to bring together researchers and practitioners from the networking, systems, and programming-language, HPC, and AI communities to discuss advances in communication and networking technologies, ranging from emerging interconnects and open networking protocols to communication middleware, collective communication frameworks, runtime systems, and approaches targeting programmable network devices for HPC and AI infrastructures.

The workshop covers smart and open networking technologies spanning the communication stack for HPC and AI. Particular emphasis is placed on programmability of elements in the network fabric, and on the open networking standards, protocols, and communication technologies that leverage such programmability for HPC and AI systems.

Topics of Interest:

We invite original research papers and experience reports on topics including, but not limited to:

Smart NICs, DPUs, programmable switches, and network accelerators
Open and programmable networking architectures, protocols, and standards, e.g., for transport and RDMA for high performance and low-latency networking in HPC and AI
Network architectures that feature programmable packet routing, processing, control, and topology-aware designs
Architectures, systems and runtimes for supporting in-network computing for HPC and AI
Programming models, abstractions, languages, and runtimes to support programmable networking elements for HPC and AI
Collective communication algorithms leveraging in-network compute and programmable data and control planes
Communication layers and libraries, e.g., MPI, OpenSHMEM, UCX, UCC, OFI, NCCL, RCCL, etc. tailored to programmable networking devices and open protocols
P4 and other approaches for data and control plane programming targeting communication middleware for HPC and AI
Leveraging programmable data, control, and management planes in HPC and AI runtimes and systems
Performance analysis, benchmarking, and optimization on smart and emerging networking technologies
Reliability, security, and manageability of programmable networking technologies for HPC and AI
Evaluation, simulation, modeling, and verification of in-network compute for HPC and AI
Next-generation programmable and open HPC and AI networking fabrics and communication stacks

News

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Program

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Registration

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Important Deadlines

Paper Submission Due: 8 December 2026 (AoE)

Notice of Paper Acceptance: 22 December 2026 (AoE)

Camera-ready Paper Due: 8 January 2027 (AoE)

Submission

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Proceedings

We will follow the SCA’s workshop timeline as well as peer-review practices to prepare the accepted papers to appear in the conference proceedings.

Committees

Workshop Co-chairs

Amir Raoofy, Leibniz Supercomputing Centre, Munich, Germany (amir.raoofy@tum.de)
Richard Vuduc, Georgia Tech, USA (richie@cc.gatech.edu)

Program Committee

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